1. Field of the Invention
The present invention relates to the apparatuses for testing digital integrated circuits and, more particularly, to the apparatuses for testing the dynamic noise immunity of such circuits.
2. Description of the Prior Art
It is known that electromagnetic noise may affect the behavior of a logic system because it adds to the voltage levels present on the input of the gate constituting such system and may alter the output of some logic gates. A distinction between two types of noise is required: the former generated outside the logic system (for instance, due to high frequency power generators operating in the vicinity) and the latter generated inside the same logic system (for instance, due to mutual couplings among leads on which logic signals are conveyed). Generally, the manufacturers of digital integrated circuits characterize a logic family through two parameters: the static noise immunity and the dynamic noise family.
The static noise immunity characterizes the behavior of a logic family disturbed by noise pulses which last longer than the average propagation delay time of such family; the static noise immunity defines the voltage levels which do not influence the logic state and is derived from the transfer function of the logic family.
The dynamic noise immunity characterizes the behavior of a logic family disturbed by noise pulses having a shorter duration than the signal propagation delay time of such family. In this case, the energy of the noise pulse (amplitude and duration) determines whether a change of the output logic state will take place.
The dynamic noise immunity is a function of the logic swing of the family and therefore varies according to such swing. Generally, for each family of gates, the manufacturers provide two typical boundary characteristics for the dynamic noise; the former refers to noise pulses disturbing an input logic level "1"; the latter refers to noise pulses disturbing an input logic level "0". Such characteristics are determined by the manufacturers through the behavior testing of a suitable sample of the logic gates. Referring to a gate, each point of the dynamic noise boundary characteristic with gate inputs at logic level 0 (or 1 as the case may be) is obtained by applying to gate inputs a positive (or negative as the case may be) noise pulse having a predetermined duration x and by varying the pulse amplitude up to a level y at which the gate output changes its logic state. The point defined by abscissa x and ordinate y is a point of the boundary characteristic. However, it is clear that the so-obtained characteristics do not take into sufficient consideration the influence that a variation of the gate logic swing has on them. In fact, the logic swing varies as a function of: the temperature, the supply voltages, the aging, the load, and so on. Consequently, the dynamic noise immunity tends to vary.
At present, during the qualification phase of digital integrated circuits, only static immunity noise is generally tested. This is obtained through the use of complex equipment, mainly devoted to test the logic function of the integrated circuit, by applying the boundary voltage levels corresponding to logic 0 and 1 to the inputs of the circuit under test and checking the output voltage levels. An example of such equipment is provided in "Electrical Engineering in Japan" vol. 89, N. 8, 1969, pp. 45-53.
At present, a comprehensive procedure for the qualification of digital integrated circuit for dynamic noise is unavailable. Until now, the dynamic noise generated inside a system has been considered a negligible problem in comparison to that caused by external noise. However, there are some cases where the dynamic noise, due to the mutual coupling among leads, assumes a considerable importance, as for instance in those applications where long transmission lines are required between the source of digital signals and the receiver.
Referring specifically to a digital transmission system, the system immunity to the dynamic noise is generally established at design level by providing in the receiving circuits some integration capacitors which increase the propagation delay time of the receiving circuit. However, these limit the operative rate of the system.
There are some cases where such limit is unacceptable, as for instance in case of very large printed circuits on which a very fast logic unit is built and where a considerable electromagnetic coupling may exist among very long leads on which logic information is conveyed. In such a situation, in order to have a high reliability of the logic system, it is necessary to qualify the used integrated circuits as to the dynamic noise, that is, to make sure that they have a predetermined dynamic noise immunity, which may be specified by the manufacturers and based on design rules generally used by engineers when designing logic systems.
A method for qualifying a digital integrated circuit as to the dynamic noise could consist in feeding the inputs with noise pulses having a predetermined amplitude and duration and then checking, by means of comparators, if the voltage pulses on the outputs of the circuit exceed a predetermined threshold corresponding to the maximum value for the logic level 0 or fall below a predeterminate threshold corresponding to the minimum voltage value for the logic level 1. In other words, the dynamic noise immunity in the presence of a predetermined minimum logic swing would be tested. However, as the duration of the output pulses approaches the propagation delay time of the digital integrated circuit under test (generally, it is a few nanoseconds) and at present, comparators having the required speed are not available on the market, it is very problematic to embody a testing apparatus operating according to the method described above.